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general description the MAX1076/max1078 are low-power, high-speed, seri- al-output, 10-bit, analog-to-digital converters (adcs) that operate at up to 1.8msps and have an internal reference. these devices feature true-differential inputs, offering bet- ter noise immunity, distortion improvements, and a wider dynamic range over single-ended inputs. a standard spi/qspi/microwire interface provides the clock necessary for conversion. these devices easily interface with standard digital signal processor (dsp) synchronous serial interfaces. the MAX1076/max1078 operate from a single +4.75v to +5.25v supply voltage. the MAX1076/max1078 include a 4.096v internal reference. the MAX1076 has a unipolar analog input, while the max1078 has a bipolar analog input. these devices feature a partial power-down mode and a full power-down mode for use between conver- sions, which lower the supply current to 2ma (typ) and 1? (max), respectively. also featured is a separate power-supply input (v l ), which allows direct interfacing to +1.8v to v dd digital logic. the fast conversion speed, low-power dissipation, excellent ac performance, and dc accuracy (?.5 lsb inl) make the MAX1076/max1078 ideal for industrial process control, motor control, and base-station applications. the MAX1076/max1078 come in a 12-pin tqfn pack- age, and are available in the commercial (0? to +70?) and extended (-40? to +85?) temperature ranges. applications data acquisition communications bill validation portable instruments motor control features ? 1.8msps sampling rate ? only 50mw (typ) power dissipation ? only 1a (max) shutdown current ? high-speed, spi-compatible, 3-wire serial interface ? 61db s/(n + d) at 525khz input frequency ? internal true-differential track/hold (t/h) ? internal 4.096v reference ? no pipeline delays ? small 12-pin tqfn package MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference ________________________________________________________________ maxim integrated products 1 12 ain+ 11 n.c. 10 sclk 45 n.c. 6 gnd 1 2 ref 3 9 8 7 rgnd cnvst dout v l MAX1076 max1078 ain- v dd tqfn top view part temp range pin- package input MAX1076 ctc-t 0 c to +70 c 12 tqfn-12 unipolar MAX1076etc-t -40 c to +85 c 12 tqfn-12 unipolar max1078 ctc-t 0 c to +70 c 12 tqfn-12 bipolar max1078etc-t -40 c to +85 c 12 tqfn-12 bipolar pin configuration ordering information MAX1076 max1078 dout ain+ 4.7 f 10 f 10 f +4.75v to +5.25v 0.01 f 0.01 f 0.01 f +1.8v to v dd ain- ref v dd differential input voltage rgnd v l gnd cnvst sclk c/dsp + - t ypical operating circuit 19-3291; rev 0; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5v ?%, v l = v dd , f sclk = 28.8mhz, 50% duty cycle, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v v l to gnd ................-0.3v to the lower of (v dd + 0.3v) and +6v digital inputs to gnd .................-0.3v to the lower of (v dd + 0.3v) and +6v digital output to gnd ....................-0.3v to the lower of (v l + 0.3v) and +6v analog inputs and ref to gnd..........-0.3v to the lower of (v dd + 0.3v) and +6v rgnd to gnd .......................................................-0.3v to +0.3v maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 12-pin tqfn (derate 16.9mw/? above +70?) ......1349mw operating temperature ranges max107_ ctc ...................................................0? to +70? max107_ etc.................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution 10 bits relative accuracy inl (note 1) ?.5 lsb differential nonlinearity dnl (note 2) ?.5 lsb offset error ? lsb offset-error temperature coefficient ? ppm/? gain error offset nulled ? lsb gain temperature coefficient ? ppm/? dynamic specifications (f in = 525khz sine wave, v in = v ref , unless otherwise noted.) signal-to-noise plus distortion sinad 60 61 db total harmonic distortion thd up to the 5th harmonic -80 -74 db spurious-free dynamic range sfdr -80 -74 db intermodulation distortion imd f in1 = 250khz, f in2 = 300khz -78 db full-power bandwidth -3db point, small-signal method 20 mhz full-linear bandwidth s/(n + d) > 56db, single ended 2 mhz conversion rate minimum conversion time t conv (note 3) 0.556 ? maximum throughput rate 1.8 msps m i ni m um thr oug hp ut rate ( n ote 4) 10 ksps track-and-hold acquisition time t acq (note 5) 104 ns aperture delay 5ns aperture jitter (note 6) 30 ps external clock frequency f sclk 28.8 mhz
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v ?%, v l = v dd , f sclk = 28.8mhz, 50% duty cycle, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units analog inputs (ain+, ain-) ain+ - ain-, MAX1076 0 v ref differential input voltage range v in ain+ - ain-, max1078 -v ref / 2 +v ref / 2 v absolute input voltage range 0 v dd v dc leakage current ? ? input capacitance per input pin 16 pf input current (average) time averaged at maximum throughput rate 75 ? reference output (ref) ref output voltage range static, t a = +25? 4.086 4.096 4.106 v voltage temperature coefficient ?0 ppm/? i source = 0 to 2ma 0.3 load regulation i sink = 0 to 200? 0.5 mv/ma line regulation v dd = 4.75v to 5.25v, static 0.5 mv/v digital inputs (sclk, cnvst) input-voltage low vil 0.3 x v l v input-voltage high vih 0.7 x v l v input leakage current i il 0.05 ?0 ? digital output (dout) output load capacitance c out for stated timing performance 30 pf output-voltage low v ol i sink = 5ma, v l 1.8v 0.4 v output-voltage high v oh i source = 1ma, v l 1.8v v l - 0.5v v output leakage current i ol output high impedance ?.2 ?0 ? power requirements analog supply voltage v dd 4.75 5.25 v digital supply voltage v l 1.8 v dd v static, f sclk = 28.8mhz 811 static, no sclk 5 7 analog supply current, normal mode i dd operational, 1.8msps 10 13 ma f sclk = 28.8mhz 2 analog supply current, partial power-down mode i dd no sclk 2 ma f sclk = 28.8mhz 1 analog supply current, full power-down mode i dd no sclk 0.3 1 ? operational, full-scale input at 1.8msps 1 2.5 static, f sclk = 28.8mhz 0.4 1 partial/full power-down mode, f sclk = 28.8mhz 0.2 0.5 ma digital supply current (note 7) static, no sclk (all modes) 0.1 1a positive-supply rejection psr v dd = 5v ?%, full-scale input ?.2 ?.0 mv
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 4 _______________________________________________________________________________________ note 1: relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offs et error have been nulled. note 2: no missing codes over temperature. note 3: conversion time is defined as the number of clock cycles (16) multiplied by the clock period. note 4: at sample rates below 10ksps, the input full-linear bandwidth is reduced to 5khz. note 5: the listed value of three sclk cycles is given for full-speed continuous conversions. acquisition time begins on the 14th ris- ing edge of sclk and terminates on the next falling edge of cnst. the ic idles in acquisition mode between conversions. note 6: undersampling at the maximum signal bandwidth requires the minimum jitter spec for sinad performance. note 7: digital supply current is measured with the v ih level equal to v l , and the v il level equal to gnd. timing characteristics (v dd = +5v ?%, v l = v dd , f sclk = 28.8mhz, 50% duty cycle, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units sclk pulse-width high t ch v l = 1.8v to v dd 15.6 ns sclk pulse-width low t cl v l = 1.8v to v dd 15.6 ns c l = 30pf, v l = 4.75v to v dd 14 c l = 30pf, v l = 2.7v to v dd 17 sclk rise to dout transition t dout c l = 30pf, v l = 1.8v to v dd 24 ns dout remains valid after sclk t dhold v l = 1.8v to v dd 4ns cnvst fall to sclk fall t setup v l = 1.8v to v dd 10 ns cnvst pulse width t csw v l = 1.8v to v dd 20 ns power-up time; full power-down t pwr-up 2ms restart time; partial power-down t rcv 16 cycles cnvst sclk dout t dhold t dout t setup t csw t cl t ch figure 1. detailed serial-interface timing gnd 6k ? c l dout dout c l gnd v l a) high-z to v oh , v ol to v oh , and v oh to high-z b) high-z to v ol , v oh to v ol , and v ol to high-z 6k ? figure 2. load circuits for enable/disable times
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference _______________________________________________________________________________________ 5 t ypical operating characteristics (v dd = +5v, v l = v dd , f sclk = 28.8mhz, f sample = 1.8msps, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) integral nonlinearity vs. digital output code (MAX1076) MAX1076/78 toc01 digital output code inl (lsb) 756 512 256 -0.1 0 0.1 0.2 -0.2 0 1024 integral nonlinearity vs. digital output code (max1078) MAX1076/78 toc02 digital output code inl (lsb) 256 0 -256 -0.1 0 0.1 0.2 -0.2 -512 512 differential nonlinearity vs. digital output code (MAX1076) MAX1076/78 toc03 digital output code inl (lsb) 756 512 256 -0.1 0 0.1 0.2 -0.2 0 1024 differential nonlinearity vs. digital output code (max1078) MAX1076/78 toc04 digital output code inl (lsb) 256 0 -256 -0.1 0 0.1 0.2 -0.2 -512 512 offset error vs. temperature (MAX1076) MAX1076/78 toc05 temperature ( c) offset error (lsb) 60 35 10 -15 -0.25 0 0.25 0.50 -0.50 -40 85 offset error vs. temperature (max1078) MAX1076/78 toc06 temperature ( c) offset error (lsb) 60 35 10 -15 -0.25 0 0.25 0.50 -0.50 -40 85 gain error vs. temperature (MAX1076) MAX1076/78 toc07 temperature ( c) gain error (lsb) 60 35 -15 10 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 -40 85 gain error vs. temperature (max1078) MAX1076/78 toc08 temperature ( c) gain error (lsb) 60 35 -15 10 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 -40 85 dynamic performance vs. input frequency (MAX1076) MAX1076/78 toc09 analog input frequency (khz) dynamic performance (db) 400 300 200 61.1 61.2 61.3 61.4 61.5 61.6 61.0 100 500 snr sinad
v dd /v l full power-down supply current vs. temperature MAX1076/78 toc18 temperature ( c) v dd /v l supply current ( a) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 0 -40 85 v dd , f sclk = 28.8mhz v dd , no sclk v l , no sclk t ypical operating characteristics (continued) (v dd = +5v, v l = v dd , f sclk = 28.8mhz, f sample = 1.8msps, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 6 _______________________________________________________________________________________ dynamic performance vs. input frequency (max1078) MAX1076/78 toc10 analog frequency (khz) dynamic performance (db) 400 300 200 61.25 61.50 61.75 62.00 61.00 100 500 snr sinad thd vs. input frequency MAX1076/78 toc11 analog input frequency (khz) thd (db) 400 300 200 -94 -92 -90 -86 -88 -84 -80 -82 -96 100 500 MAX1076 max1078 sfdr vs. input frequency MAX1076/78 toc12 analog input frequency (khz) sfdr (db) 400 300 200 84 86 88 90 82 100 500 max1078 MAX1076 fft plot (MAX1076) MAX1076/78 toc13 analog frequency (khz) amplitude (db) 750 600 450 300 150 -120 -100 -80 -60 -40 -20 0 -140 0 900 f in = 500khz sinad = 61.5db snr = 61.4db thd = -88.5db sfdr = 87.0db fft plot (max1078) MAX1076/78 toc14 analog frequency (khz) amplitude (db) 750 600 450 300 150 -120 -100 -80 -60 -40 -20 0 -140 0 900 f in = 500khz sinad = 61.4db snr = 61.5db thd = -93.8db sfdr = 84.5db total harmonic distortion vs. source impedance MAX1076/78 toc15 source impedance ( ? ) thd (db) 100 -90 -80 -70 -60 -50 -100 10 1000 f in = 500khz f in = 100khz two-tone imd plot (MAX1076) MAX1076/78 toc16 analog frequency (khz) amplitude (db) 800 600 400 200 -120 -100 -80 -60 -40 -20 0 -140 0 1000 f sample = 2msps f in1 = 250.039khz f in2 = 300.059khz imd = -81.9db f in1 f in2 two-tone imd plot (max1078) MAX1076/78 toc17 analog frequency (khz) amplitude (db) 800 600 400 200 -120 -100 -80 -60 -40 -20 0 -140 0 1000 f sample = 2msps f in1 = 250.039khz f in2 = 300.059khz imd = 82.1db f in1 f in2
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference _______________________________________________________________________________________ 7 v l partial/full power-down supply current vs. temperature MAX1076/78 toc19 temperature ( c) v l supply current ( a) 60 35 10 -15 50 100 150 200 0 -40 85 v l = 5v, f sclk = 28.8mhz v l = 3v, f sclk = 28.8mhz v dd supply current vs. temperature MAX1076/78 toc20 temperature ( c) v dd supply current (ma) 60 35 10 -15 3 6 9 12 0 -40 85 conversion, f sclk = 28.8mhz partial power-down v dd supply current vs. conversion rate MAX1076/78 toc21 f sample (khz) v dd supply current (ma) 1500 1000 500 3 6 9 12 0 0 2000 v l supply current vs. temperature MAX1076/78 toc22 temperature ( c) v l supply current (ma) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 0 -40 85 conversion, f sclk = 28.8mhz full/partial power-down, f sclk = 28.8mhz v l supply current vs. conversion rate MAX1076/78 toc23 f sample (khz) v l supply current (ma) 1500 1000 500 0.2 0.4 0.6 0.8 1.0 0 0 2000 v l = 5v v l = 3v v l = 1.8v reference voltage vs. temperature MAX1076/78 toc24 temperature ( c) reference voltage (v) 60 35 10 -15 4.08 4.10 4.12 4.06 -40 85 reference voltage vs. load current (source) MAX1076/78 toc25 load current (ma) reference voltage (v) 8 6 4 2 4.07 4.08 4.09 4.10 4.06 010 reference voltage vs. load current (sink) MAX1076/78 toc26 load current ( a) reference voltage (v) 400 300 200 100 4.09 4.10 4.11 4.12 4.08 0 500 t ypical operating characteristics (continued) (v dd = +5v, v l = v dd , f sclk = 28.8mhz, f sample = 1.8msps, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.)
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 8 _______________________________________________________________________________________ pin description pin name function 1 ain- negative analog input 2 ref reference voltage output. internal 4.096v reference output. bypass ref with a 0.01? capacitor and a 4.7? capacitor to rgnd. 3 rgnd reference ground. connect rgnd to gnd. 4v dd positive analog supply voltage (+4.75v to +5.25v). bypass v dd with a 0.01? capacitor and a 10? capacitor to gnd. 5, 11 n.c. no connection 6 gnd ground. gnd is internally connected to ep. 7v l positive logic supply voltage (1.8v to v dd ). bypass v l with a 0.01? capacitor and a 10? capacitor to gnd. 8 dout serial data output. data is clocked out on the rising edge of sclk. 9 cnvst convert start. forcing cnvst high prepares the part for a conversion. conversion begins on the falling edge of cnvst. the sampling instant is defined by the falling edge of cnvst. 10 sclk serial clock input. clocks data out of the serial interface. sclk also sets the conversion speed. 12 ain+ positive analog input ? p exposed paddle. ep is internally connected to gnd. detailed description the MAX1076/max1078 use an input t/h and succes- sive-approximation register (sar) circuitry to convert an analog input signal to a digital 10-bit output. the serial interface requires only three digital lines (sclk, cnvst, and dout) and provides easy interfacing to microprocessors (?s) and dsps. figure 3 shows the simplified internal structure for the MAX1076/max1078. true-differential analog input t/h the equivalent circuit of figure 4 shows the input archi- tecture of the MAX1076/max1078, which is composed of a t/h, a comparator, and a switched-capacitor digital-to- analog converter (dac). the t/h enters its tracking mode on the 14th sclk rising edge of the previous conversion. upon power-up, the t/h enters its tracking mode immedi- ately. the positive input capacitor is connected to ain+. the negative input capacitor is connected to ain-. the t/h enters its hold mode on the falling edge of cnvst and the difference between the sampled positive and negative input voltages is converted. the time required for the t/h to acquire an input signal is determined by how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens. the acquisition time, t acq , is the minimum time needed for the signal to be acquired. it is calculated by the following equation: t acq 8 (rs + r in ) 16pf where r in = 200 ? , and rs is the source impedance of the input signal. note: t acq is never less than 104ns, and any source impedance below 12 ? does not significantly affect the adc? ac performance. input bandwidth the adc? input-tracking circuitry has a 20mhz small- signal bandwidth, making it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input protection internal protection diodes that clamp the analog input to v dd and gnd allow the analog input pins to swing from gnd - 0.3v to v dd + 0.3v without damage. both inputs must not exceed v dd or be lower than gnd for accurate conversions.
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference _______________________________________________________________________________________ 9 serial interface initialization after power-up and starting a conversion upon initial power-up, the MAX1076/max1078 require a complete conversion cycle to initialize the internal cali- bration. following this initial conversion, the part is ready for normal operation. this initialization is only required after a hardware power-up sequence and is not required after exiting partial or full power-down mode. to start a conversion, pull cnvst low. at cnvst? falling edge, the t/h enters its hold mode and a con- version is initiated. sclk runs the conversion and the data can then be shifted out serially on dout. timing and control conversion-start and data-read operations are con- trolled by the cnvst and sclk digital inputs. figures 1 and 5 show timing diagrams, which outline the serial- interface operation. a cnvst falling edge initiates a conversion sequence: the t/h stage holds the input voltage, the adc begins to convert, and dout changes from high impedance to logic low. sclk is used to drive the conversion process, and it shifts data out as each bit of the con- version is determined. sclk begins shifting out the data after the 4th rising edge of sclk. dout transitions t dout after each sclk? rising edge and remains valid 4ns (t dhold ) after the next rising edge. the 4th rising clock edge produces the msb of the conversion at dout, and the msb remains valid 4ns after the 5th rising edge. since there are 10 data bits, 2 sub-bits (s1 and s0), and 3 leading zeros, at least 16 rising clock edges are need- ed to shift out these bits. for continuous operation, pull cnvst high between the 14th and the 16th sclk ris- ing edges. if cnvst stays low after the falling edge of the 16th sclk cycle, the dout line goes to a high- impedance state on either cnvst? rising edge or the next sclk? rising edge. partial power-down and full power-down modes power consumption can be reduced significantly by placing the MAX1076/max1078 in either partial power- down mode or full power-down mode. partial power- down mode is ideal for infrequent data sampling and fast wake-up time applications. pull cnvst high after the 3rd sclk rising edge and before the 14th sclk rising edge to enter and stay in partial power-down mode (see figure 6). this reduces the supply current to 2ma. while in partial power-down mode, the refer- ence remains enabled to allow valid conversions once the ic is returned to normal mode. drive cnvst low and allow at least 14 sclk cycles to elapse before dri- ving cnvst high to exit partial power-down mode. full power-down mode is ideal for infrequent data sam- pling and very low supply-current applications. the MAX1076/max1078 have to be in partial power-down mode in order to enter full power-down mode. perform the sclk/cnvst sequence described above to enter rgnd ain+ gnd dout sclk cnvst control logic and timing ain- v l v dd ref 10-bit sar adc MAX1076 max1078 t/h output buffer ref 4.096v figure 3. functional diagram c in+ r in+ r in- c in- v az ain+ ain- control logic capacitive dac comp acquisition mode c in+ r in+ r in- c in- v az ain+ ain- control logic capacitive dac comp hold/conversion mode figure 4. equivalent input circuit
MAX1076/max1078 partial power-down mode. then repeat the same sequence to enter full power-down mode (see figure 7). drive cnvst low, and allow at least 14 sclk cycles to elapse before driving cnvst high to exit full power- down mode. while in full power-down mode, the refer- ence is disabled to minimize power consumption. be sure to allow at least 2ms recovery time after exiting full power-down mode for the reference to settle. in partial/full power-down mode, maintain a logic low or a logic high on sclk to minimize power consumption. transfer function figure 8 shows the unipolar transfer function for the MAX1076. figure 9 shows the bipolar transfer function for the max1078. the MAX1076 output is straight binary, while the max1078 output is two? complement. 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 10 ______________________________________________________________________________________ dout mode sclk cnvst dout goes high impedance once cnvst goes high cnvst must go high after the 3rd but before the 14th sclk rising edge one 8-bit transfer 1st sclk rising edge ppd 000d9d8d 7d6 d5 normal ref enabled (4.096v) figure 6. spi interface?artial power-down mode figure 5. interface-timing sequence figure 7. spi interface?ull power-down mode t acquire continuous-conversion selection window cnvst t setup dout sclk 414 12 8 3 16 high impedance s1 d2 d4 d3 d7 d6 d5 d9 d8 power-mode selection window s0 d0 d1 1st sclk rising edge 1st sclk rising edge 000d9d8d 7d6 d5 dout mode sclk cnvst 000 000 0 fpd disabled recovery ppd normal 0 dout enters tri-state once cnvst goes high execute partial power-down twice first 8-bit transfer second 8-bit transfer ref enabled (4.096v)
applications information internal reference the MAX1076/max1078 have an on-chip voltage refer- ence trimmed to 4.096v. the internal reference output is connected to ref and also drives the internal capac- itive dac. the output can be used as a reference volt- age source for other components and can source up to 2ma. bypass ref with a 0.01? capacitor and a 4.7? capacitor to rgnd. the internal reference is continuously powered up dur- ing both normal and partial power-down modes. in full power-down mode, the internal reference is disabled. be sure to allow at least 2ms recovery time after hard- ware power-up or exiting full power-down mode for the reference to reach its intended value. how to start a conversion an analog-to-digital conversion is initiated by cnvst and clocked by sclk, and the resulting data is clocked out on dout by sclk. with sclk idling high or low, a falling edge on cnvst begins a conversion. this causes the analog input stage to transition from track to hold mode, and dout to transition from high impedance to being actively driven low. a total of 16 sclk cycles are required to complete a normal conversion. if cnvst is low during the 16th falling sclk edge, dout returns to high impedance on the next rising edge of cnvst or sclk, enabling the serial interface to be shared by multi- ple devices. if cnvst returns high after the 14th, but before the 16th sclk rising edge, dout remains active so continuous conversions can be sustained. the high- est throughput is achieved when performing continuous conversions. figure 10 illustrates a conversion using a typical serial interface. connection to standard interfaces the MAX1076/max1078 serial interface is fully compati- ble with spi/qspi and microwire (see figure 11). if a serial interface is available, set the cpu? serial interface in master mode so the cpu generates the serial clock. choose a clock frequency up to 28.8mhz. spi and microwire when using spi or microwire, the MAX1076/max1078 are compatible with all four modes programmed with the cpha and cpol bits in the spi or microwire control register. conversion begins with a cnvst falling edge. dout goes low, indicating a conversion is in progress. two consecutive 1-byte reads are required to get the full 10 bits from the adc. dout transitions on sclk rising edges. dout is guaranteed to be valid t dout later and MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference ______________________________________________________________________________________ 11 output code full-scale transition 111...111 12 3 0 fs fs - 3/2 lsb fs = v ref differential input voltage (lsb) 1 lsb = v ref 1024 111...110 111...101 000...011 000...010 000...001 000...000 zs = 0 figure 8. unipolar transfer function (MAX1076 only) output code full-scale transition fs 0 -fs fs - 3/2 lsb differential input voltage (lsb) 011...111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 1 lsb = v ref 1024 fs = v ref 2 - fs = -v ref 2 zs = 0 figure 9. bipolar transfer function (max1078 only)
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 12 ______________________________________________________________________________________ 000d9d8d 7d6d 5d4d3d2d1d0s1s0 0 dout sclk cnvst 0 1 1 16 14 figure 10. continuous conversion with burst/continuous clock figure 11. common serial-interface connections to the MAX1076/max1078 MAX1076 max1078 +3v to +5v cnvst sclk dout i/o sck miso ss a) spi MAX1076 max1078 +3v to +5v cnvst sclk dout cs sck miso ss b) qspi MAX1076 max1078 cnvst sclk dout i/o sk si c) microwire
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference ______________________________________________________________________________________ 13 remains valid until t dhold after the following sclk rising edge. when using cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1, the data is clocked into the ? on the following rising edge. when using cpol = 0 and cpha = 1 or cpol = 1 and cpha = 0, the data is clocked into the ? on the next falling edge. see figure 11 for connections and figures 12 and 13 for timing. see the timing characteristics section to determine the best mode to use. qspi unlike spi, which requires two 1-byte reads to acquire the 10 bits of data from the adc, qspi allows the mini- mum number of clock cycles necessary to clock in the data. the MAX1076/max1078 require 16 clock cycles from the ? to clock out the 10 bits of data. figure 14 shows a transfer using cpol = 1 and cpha = 1. the conversion result contains three zeros, followed by the 10 data bits, 2 sub-bits, and a trailing zero with the data in msb-first format. dsp interface to the tms320c54_ the MAX1076/max1078 can be directly connected to the tms320c54_ family of dsps from texas instruments, inc. set the dsp to generate its own clocks or use external clock signals. use either the standard or buffered serial port. figure 15 shows the simplest interface between the MAX1076/max1078 and sclk dout 916 8 1 d0 d9 d8 d6 d5 d4 d3 d2 d1 d7 high-z high-z cnvst s1 s0 figure 13. spi/microwire serial-interface timing?ontinuous conversion (cpol = cpha = 0), (cpol = cpha = 1) 000d9d 8d7d6d5d4d3d 2d1d0s1s0 0 dout sclk cnvst 0 1 1 14 16 figure 12. spi/microwire serial-interface timing?ingle conversion (cpol = cpha = 0), (cpol = cpha = 1) figure 14. qspi serial-interface timing?ingle conversion (cpol = 1, cpha = 1) sclk dout cnvst 16 s0 s1 d9 d8 d4 d5 d6 d3 d2 d1 d0 high-z d7 high-z 2
the tms320c54_, where the transmit serial clock (clkx) drives the receive serial clock (clkr) and sclk, and the transmit frame sync (fsx) drives the receive frame sync (fsr) and cnvst. for continuous conversion, set the serial port to trans- mit a clock, and pulse the frame sync signal for a clock period before data transmission. the serial-port config- uration (spc) register should be set up with internal frame sync (txm = 1), clkx driven by an on-chip clock source (mcm = 1), burst mode (fsm = 1), and 16-bit word length (fo = 0). this setup allows continuous conversions provided that the data-transmit register (dxr) and the data-receive register (drr) are serviced before the next conversion. alternatively, autobuffering can be enabled when using the buffered serial port to execute conversions and read the data without cpu intervention. connect the v l pin to the tms320c54_ supply voltage when the MAX1076/max1078 are operating with an analog sup- ply voltage higher than the dsp supply voltage. the word length can be set to 8 bits with fo = 1 to imple- ment the power-down modes. the cnvst pin must idle high to remain in either power-down state. another method of connecting the MAX1076/max1078 to the tms320c54_ is to generate the clock signals external to either device. this connection is shown in figure 16 where serial clock (clock) drives the clkr and sclk and the convert signal (convert) drives the fsr and cnvst. the serial port must be set up to accept an external receive-clock and external receive-frame sync. the spc register should be written as follows: txm = 0, external frame sync mcm = 0, clkx is taken from the clkx pin fsm = 1, burst mode fo = 0, data transmitted/received as 16-bit words this setup allows continuous conversion, provided that the drr is serviced before the next conversion. alternatively, autobuffering can be enabled when using the buffered serial port to read the data without cpu intervention. connect the v l pin to the tms320c54_ supply voltage when the MAX1076/max1078 are oper- ating with an analog supply voltage higher than the dsp supply voltage. the MAX1076/max1078 can also be connected to the tms320c54_ by using the data transmit (dx) pin to drive cnvst and the clkx generated internally to drive sclk. a pullup resistor is required on the cnvst signal to keep it high when dx goes high impedance and 0001hex should be written to the dxr continuously for continuous conversions. the power-down modes may be entered by writing 00ffhex to the dxr (see figures 17 and 18). dsp interface to the adsp21_ _ _ the MAX1076/max1078 can be directly connected to the adsp21_ _ _ family of dsps from analog devices, inc. figure 19 shows the direct connection of the MAX1076/max1078 to the adsp21_ _ _. there are two modes of operation that can be programmed to interface with the MAX1076/max1078. for continuous conver- sions, idle cnvst low and pulse it high for one clock cycle during the lsb of the previous transmitted word. the adsp21_ _ _ stctl and srctl registers should be configured for early framing (lafr = 0) and for an active-high frame (ltfs = 0, lrfs = 0) signal. in this mode, the data-independent frame-sync bit (ditfs = 1) MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 14 ______________________________________________________________________________________ figure 15. interfacing to the tms320c54_ internal clocks figure 16. interfacing to the tms320c54_ external clocks MAX1076 max1078 tms320c54_ v l sclk cnvst dout dv dd clkr fsr clkx fsx dr MAX1076 max1078 tms320c54_ v l dv dd sclk clkr cnvst fsr dout dr clock convert
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference ______________________________________________________________________________________ 15 can be selected to eliminate the need for writing to the transmit-data register more than once. for single conver- sions, idle cnvst high and pulse it low for the entire conversion. the adsp21_ _ _ stctl and srctl regis- ters should be configured for late framing (lafr = 1) and for an active-low frame (ltfs = 1, lrfs = 1) signal. this is also the best way to enter the power-down modes by setting the word length to 8 bits (slen = 1001). connect the v l pin to the adsp21_ _ _ supply voltage when the MAX1076/max1078 are operating with a sup- ply voltage higher than the dsp supply voltage (see figures 17 and 18). layout, grounding, and bypassing for best performance, use pc boards. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separat- ed from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 20 shows the recommended system ground connections. establish a single-point analog ground (star ground point) at gnd, separate from the logic ground. connect all other analog grounds and dgnd to this star ground point for further noise reduction. the ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply can affect the adc? high-speed comparator. bypass this supply to the single-point analog ground with 0.01? and 10? bypass capacitors. minimize capacitor lead lengths for best supply-noise rejection. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the MAX1076/max1078 are mea- sured using the end-points method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of 1 lsb or less guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. 000d9d8d7d 6d5d 4d3d2d 1d0s1s0 0 dout sclk cnvst 0 0 s0 1 1 figure 17. dsp interface?ontinuous conversion 000d9d8d7d6d5d 4d3 d2 d 1d0s1s0 0 dout sclk cnvst 0 0 1 1 figure 18. dsp interface?ingle-conversion, continuous/burst clock
MAX1076/max1078 aperture delay aperture delay (t ad ) is the time defined between the falling edge of cnvst and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital sam- ples, signal-to-noise ratio (snr) is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the adc? resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quantiza- tion noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all other adc output signals: sinad(db) = 20 x log (signal rms / noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantiza- tion noise only. with an input range equal to the full-scale range of the adc, calculate the enob as follows: total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest distor- tion component. full-power bandwidth full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3db for a full-scale input. thd x v vvv v log = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 enob sinad ( .) . = ? 176 602 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference 16 ______________________________________________________________________________________ MAX1076 max1078 adsp21_ _ _ v l sclk cnvst dout vddint rclk rfs tclk tfs dr figure 19. interfacing to the adsp21_ _ _ 10 f 0.1 f 10 f 0.1 f v dd gnd v l supplies dgnd v l digital circuitry v dd gnd rgnd v l MAX1076 max1078 figure 20. power-supply grounding condition
full-linear bandwidth full-linear bandwidth is the frequency at which the sig- nal-to-noise plus distortion (sinad) is equal to 56db. intermodulation distortion any device with nonlinearities creates distortion prod- ucts when two sine waves at two different frequencies (f1 and f2) are input into the device. intermodulation distortion (imd) is the total power of the im2 to im5 intermodulation products to the nyquist frequency rela- tive to the total input power of the two input tones, f1 and f2. the individual input tone levels are at -7dbfs. the intermodulation products are as follows: 2nd-order intermodulation products (im2): f 1 + f 2 , f 2 - f 1 3rd-order intermodulation products (im3): 2f 1 - f 2 , 2f 2 - f 1 , 2f 1 + f 2 , 2f 2 + f 1 4th-order intermodulation products (im4): 3f 1 - f 2 , 3f 2 - f 1 , 3f 1 + f 2 , 3f 2 + f 1 5th-order intermodulation products (im5): 3f 1 - 2f 2 , 3f 2 - 2f 1 , 3f 1 + 2f 2 , 3f 2 + 2f 1 MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference ______________________________________________________________________________________ 17 chip information transistor count: 13,016 process: bicmos
MAX1076/max1078 1.8msps, single-supply, low-power, true- differential, 10-bit adcs with internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps c 1 2 21-0139 package ? outline 12, ? 16, ? 20, ? 24l ? thin ? qfn, ? 4x4x0.8mm c 2 2 21-0139 package ? outline 12, ? 16, ? 20, ? 24l ? thin ? qfn, ? 4x4x0.8mm

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